Early Clock Tree Estimation for QOR Improvement in Soc Design

This paper gives the Growth of the semiconductor industry has made the design of integrated circuits in daunting task. The ASIC design flow is differs the design of the clock network until late in the design of cycle when the cell placement is done and the location of the registers are known. And the clock tree estimation always based on best guess of the ASIC planner. In additional the critical elements such as power, latency and uncommon buffer in synchronized clock network will affect the performance as well as power definition if the ASIC fullchip specifications. In this paper shows the relationship in terms of clock skew, clock network latency and clock network power with respect to floor planning aspect ratio, register count, design utilization and clock tree synthesis constraint. In this paper we examine the design factors that affect the implementation, design and optimization of ASIC design. Here we focus on implementation and design of the power, timing specifications and clock network as three most important signal in the design, and study the various electrical and the physical factors that affect their performance and reliability. The proposed ASIC planner relies on designing a hybrid clock network that provides reducing the power, timing specification, predictability and robustness to the design flow. Key terms: Clock Network, ASIC Floor-planning.